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AR# 33531

11.3 Spartan-6 FPGA Place - Automatic clock placement fails for design that should place easily


My design fails with an error indicating that "automatic clock placement" failed. The design is small and should not be difficult to place. What are the possible reasons for this failure?

ERROR:Place:1163 - Automatic clock placement failed. Please attempt to analyze
the global clocking required for this design and either lock the clock
placement or area locate the logic driven by the clocks so that the
clocks may be placed in such a way that all logic driven by them may be
routed. There are two main restrictions on clock placement for this
architecture. The first is that is that only 16 of all clocks sourced by
BUFGs, PLL, and DCMs may enter a region. For further information see the
"Clock Resources" section in the S-6 User Guide.


Automatic clock placement is a two phase process. First, all clock components and their associated I/O components are placed, and then a second phase is run to constrain clock loads to locations that can be reached by the clock components. This usually involves area constraining the clock domains to one or more clock regions.

In general, when automatic clock placement fails, the reason can be one of several things:
- a poor selection was made for the clock component placement
- a poor clock region allocation was made for one or more clock domains
- the clock structure is very complex and a placement solution is difficult or impossible to find

A specific case has been seen where the clock placer chose a DCM site that was in a clock region that did not have enough bonded I/O sites for the I/O components driven by the DCM. A fix for this specific issue is scheduled for ISE revision 11.4. Meanwhile, a work around for this and similar clock placement issues is to floorplan the clock components so that any such conflicts are avoided.
AR# 33531
Date 02/07/2013
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • ISE Design Suite - 11.3
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