The Spartan-6 FPGA GTP Transceiver Wizard v1.3 allows reference clocks to be selected that are not valid in hardware. This Answer Record discusses how to calculate and confirm valid reference clocks.
When selecting a reference clock from the Spartan-6 FPGA GTP Transceiver Wizard, some clock options are derived from incorrect divider settings. The result is that clock options are presented that will not work correctly in simulation or in hardware.
To verify that the clock being used in your design is correct, the following attributes and ports need to be checked for the PLL being used and verified against the UG:
INTDATAWIDTH_x (for equations use "0" = 4, "1" = 5)
Ensure that the following equation is correct for the selected application, noting that the factor of 2 is from DDR transmission:
More specifically, the wizard may set PLL_DIVSEL_FB = 3, which is not supported. If this is the case, please select another reference clock from the Wizard drop-down menu.