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AR# 33534

Design Advisory for the Endpoint Block Plus for PCI Express Wrapper v1.12 for PCI Express - Using Synplify with the Block Plus Wrapper Source Code Delivery

Description

The v1.12 release includes source code for the Block Plus Wrapper for PCI Express. Synthesis for the wrapper source code is only supported by XST. Synplify users must synthesize the wrapper source code with XST first and then blackbox the resulting edif in their design. This flow is very much the same as previous releases where Synplify users blackboxed the generated ngc file. The difference now is the user has access to the source code and it must be pre-compiled using XST.

This flow will be automatic in the v1.13 release. Until then, this Answer Record will step users though the process for Synplify.

Solution

Follow these steps when using Synplify.

The supporting files for this flow can be found at this FTP link:

http://www.xilinx.com/txpatches/pub/applications/pci/ar33534.zip


The following steps assume that the generated core name is "endpoint_blk_plus_v1_12" and the device is XC5VLX50T-FF1136-1. If another name or device is used, the scripts will need to be modified to match.

1. Generate the Block Plus core with the generation option for flow vendor set to Synplicity.

2. Add the following commands to endpoint_blk_plus_v1_12/implement/implement.sh, after "mkdir results":

# Synthesize the wrapper files with XST
echo 'Synthesizing wrapper files with XST';
xst -ifn xst.scr
mv endpoint_blk_plus_v1_12.ngc ./results/ endpoint_blk_plus_v1_12.ngc

The zip file contains an example of this in the impl_syn.sh. This file can be used to replace the implement.sh file, but it assumes the device to be XC5VLX50T-FF1136-1, core name to be "endpoint_blk_plus_v1_12", and lane width to be x8.

3. Add the xst.scr file from the zip file into the endpoint_blk_plus_v1_12/implement/ directory. Again, this file also assumes core name to be "endpoint_blk_plus_v1_12" and the device to be XC5VLX50T-FF1136-1 and will need to be updated if another device or core name is in use.

4. From the zip file, add the new file sources_files_xst.prj to endpoint_blk_plus_v1_12/implement/. This file also assumes Core name to be "endpoint_blk_plus_v1_12".

5. In the endpoint_blk_plus_v1_12/example_design/ directory, replace the black box instance file with one of the black instance files from the zip file. The file to use depends on the lane width. This file also assumes core name to be "endpoint_blk_plus_v1_12".

6. Implement the design as usual.

Revision History
07/05/2011 - Updated title
09/18/2009 - Initial Release

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33580 Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33580 Design Advisory for the Virtex-5 FPGA Endpoint Block Plus Wrapper for PCI Express Master Answer Record N/A N/A
AR# 33534
Date Created 09/18/2009
Last Updated 05/22/2012
Status Active
Type Design Advisory
IP
  • Virtex-5 Integrated Endpoint Block