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AR# 33576

Virtex-6 MMCM, 11.3 MAP - MMCM does not lock and "ERROR:PhysDesignRules:2045" for PFD frequencies above 300 MHz with bandwidth set to LOW


In the Virtex-6 FPGA, the MMCM might not lock if the Phase Frequency Detector (PFD) is above 300 MHz while BANDWIDTH is set to LOW. ISE Design Suite implementation tools version 11.3 and later issue the following error when this condition is detected:

"ERROR:PhysDesignRules:2045 - The DIVCLK_DIVIDE value 1.000000 of MMCM_ADV instance G_MPGC[1].C_MPGC4ch/C_CLK/C_RXMMCM is below the Fin / Fpfd value 1.041667, where Fin is the input frequency, 312.500000 MHz, and Fpfd min - max values of 10.000000 - 300.000000 MHz."


If the MMCM bandwidth is set to LOW, then the maximum PFD frequency (FPFDMAX) is limited to 300 MHz. The minimum PFD frequency (FPFDMIN) specification is unaffected by the bandwidth setting. If you are selecting a bandwidth of OPTIMIZED or HIGH, the data sheet specification still applies.

If the bandwidth is set to low and the PFD frequency (CLKIN / DIVCLK_DIVIDE) is greater than 300 MHz, then the MMCM may not lock.

Revision 1.2of the Virtex-6 FPGA Data Sheet includes this information.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
32929 Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA N/A N/A
AR# 33576
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4