The VFBC interface consists of a read and a write FIFO interface, along with a shared command interface to initiate transfers.
Its main functions are to provide a rectangular DMA interface to memory (such as a video frame or sub frame) at a clock frequency unrelated to the memory clock.
Designs not requiring the asynchronous clocking ratio may also opt to use a NPI or Spartan-6 MCB port interface for simple, high-bandwidth memory interfaces to logic.
For information on designing to NPI, see the MPMC data sheet and (Xilinx Answer 24912).
The majority of the information on the VFBC interface can be found in the MPMC data sheet, primarily in the VFBC subsections of the "Design Parameters", "Signal Descriptions", and "Personality Interface Modules" sections.
A full design example is available as part of the Video Starter Kit (VSK):
Be sure to obey the address, x-size, and stride alignment requirements described in the MPMC data sheet.
If unaligned transfers are needed, consider using the VDMA core, distributed via Xilinx CORE Generator 11.3 and later.
In addition to controlling unaligned transfers to the VFBC, the VDMA also provides additional abstraction of the VFBC interface.
The VDMA provides a set of frame buffers managed by the processor through a PLB interface.
The VDMA also provides optional frame synchronization with other VDMAs.
For more information, see:
A simple VHDL template pcore is also available in the following link as a starting point:
This design provides a simple template with the VFBC interface signals and EDK pcore structure already created.
To use it, extract this zip file to an EDK project's pcore directory or custom IP repository.
The core can then be added to an EDK project.