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AR# 33589

SPI-3 Link Layer v6.1 and v7.1 - MMCM multiply and divide values for Virtex-6 FPGA example design are incorrect


The SPI-3 Link core's clocking example design ("<component_name>_top.v[hd]" file) uses incorrect MMCM multiply and divide values for the "tfmmcm" and "rfmmcm" instances. The CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F are both set such that the VCO frequency falls outside of the supported range for some speed grades. Please reference (Xilinx Answer 33849) for more information on this issue.

This does not produce an error during implementation in 11.4 and earlier, but it could cause the design to fail in hardware.


To work around this issue, set both the CLKFBOUT_MULT_F and CLKOUT0_DIVIDE_F values for the "tfmmcm" and "rfmmcm" instances accordingly so that the VCO is operating in a supported range for your speed grade.

This issue is fixed in the v7.1 Rev1 of the Core released with ISE 11.5.

Revision History
09/30/2009 - Initial Release
01/21/2010 - Updated to point to AR 33849
03/01/2010 - Updated to add fixed version

AR# 33589
Date 12/15/2012
Status Active
Type General Article