Implementing the Endpoint Block Plus core gives this warning:
"WARNING:PhysDesignRules:372 - Gated clock. Clock netI_pcie_core_wrapper/I_pci_express_wrapper/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/icdrreset<0> is sourced by a combinatorial pin. This is not a gooddesign practice. Use the CE pin to control the loading of data into theflip-flop."
Is this expected?
Note: This Answer Record is part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you are starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.
This message is expected and can be safely ignored. There is a latch implemented purposely in the wrapper logic for the MGTs.
7/30/2011 - Initial Release