My design is failing with the following "Place:1018" error. I have LOC'd the CLKIOB to a valid CLKIOB site. The BUFG is not LOC'd and for some reason the placer placed the BUFG in a Side BUFG location instead of the Top BUFG site that corresponds to the CLKIOB used. Why did the placer not use the valid BUFG site?
" ERROR:Place:1018 - A clock IOB / clock component pair have been found that are not placed at an optimal clock IOB /
clock site pair. The clock component <ETXCLK_In_BUFG> is placed at site <BUFGMUX_X0Y8>. The IO component <E_TXCLK> is
placed at site <PAD84>. This will not allow the use of the fast path between the IO and the Clock buffer. If this
sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .ucf
file to demote this message to a WARNING and allow your design to continue. However, the use of this override is
highly discouraged as it may lead to very poor timing results. It is recommended that this error condition be
corrected in the design. A list of all the COMP.PINs used in this clock placement rule is listed below. These
examples can be used directly in the .ucf file to override this clock rule.
< NET "E_TXCLK" CLOCK_DEDICATED_ROUTE = FALSE; > "
The failed clock placement can be debugged by setting the CLOCK_DEDICATED_ROUTE constraint as detailed in the error message and then run implementation again so that a placed ".ncd" file can be examined in FPGA Editor to determine what went wrong with the placement. The "Place:1018" error does not identify the root cause of the placement failure, it only identifies what is wrong with the resulting failed placement. That failed placement can be analyzed to identify what other components might have been placed in contention for the BUFG site needed for the failed circuit.
For the error message in this Answer Record, the root cause of the placement failure was that the BUFG site required for the LOC'd CLKIOB site was a Top Edge BUFG site. All four of the Top Edge BUFG sites were used by other BUFG components that were also constrained to the Top edge by CLKIOB components. The biggest source of contention was a DCM circuit with three BUFGs that was constrained to the Top Edge by a CLKIN pin LOC. The failed circuit in the error message was not incorrectly specified by itself, but lost out in a game of musical chairs since five BUFGs were constrained to the four BUFGs on the Top Edge. The solution is to move one of the CLKIOBs to another area of the device to relieve the contention.
A CR is being reviewed to provide better error handling. Ideally, the placer error would identify the source of the contention, rather than only noting what is wrong with the failed placement.