When I run timing analysis on my design, the clock skew appears to large for the simple clock topology.
This clock skew is from cross clock domain analysis. ClockA is a DCM -> BUFG -> PLL -> BUFG and ClockB is a DCM -> BUFG -> PLL -> BUFG.
When is this going to be fixed?
This issue is scheduled to be fixed in the next major release of the software, which is 11.4.