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AR# 33692

Spartan-6 FPGA - Using an IDDR and ODDR in the same I/O block gives ERROR:Route:472


Keywords: Spartan-6, DDR, 472, ERROR:Route, 472

When implementing a bidirectional pin with input DDR and output DDR in the same IOB, the following error is seen from the Place and Route tools:

ERROR:Route:472 -This design is unrouteable. To evaluate the problem please use fpga_editor.


When using DDR on both the input and output of a bidirectional pin, both must use the same clock. The reason for this error is that there are only 3 unique CLK connections in the Spartan-6 FPGA IOLOGIC, and each DDR implementation uses 2 of those dedicated connections for its CLK and CLK_INV. Therefore, an IDDR and ODDR in the same IOB of different clock rates is not achievable.
AR# 33692
Date 12/10/2009
Status Active
Type General Article