AR# 33698

MIG 7 Series and Virtex-6 FPGA DDR2/DDR3 - How do I drive the user interface?


This part of the MIG Design Assistant will guide you to information on driving the User Interface.

NOTE: This answer record is part of the Xilinx MIG Solution Center (Xilinx Answer 34243). The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.


Interfacing to the Core

The memory controller can be connected using either the User Interface (UI) or the Native Interface. The User Interface resembles a simple FIFO interface. While the controller may have reordered memory requests on the DDR bus to improve efficiency, the User Interface will always return the data in the order requested. The memory controller can be interfaced using either User Interface (UI) or Native Interface.

Native Interface

The Native Interface offers higher performance in some situations but is more challenging to use, therefore, it might require more overhead on the user application. The Native interface contains no buffers and returns data as soon as possible, but the return data might be out of order. The application must reorder the received data internally if the Native Interface is used.

The following information describes timing protocols of the User Interface and how it should be controlled.

User Interface (UI)

The physical RANK, BANK, ROW, COLUMN address scheme is abstracted in the User Interface module as shown in Figure 1. This allows a simple logical address interface.

Figure-1 Memory Address Mapping
Figure-1 Memory Address Mapping

Figure 1: Memory Address Mapping

Command Path

A command is loaded to the command FIFO by the User Interface(UI) when both user logic app_en is asserted and app_full is not asserted from the UI. A command is ignored by the UI whenever app_full is asserted. User logic needs to hold the app_en high along with the valid command and address value until the app_full is deasserted, as shown in Figure 2. Non back-to-back write commands can be given as shown in Figure 3. For write data that is given after the write command has been registered, as shown in 1c, the maximum delay is 2 clock cycles.

Figure-2 UI Command Timing with app_full Asserted
Figure-2 UI Command Timing with app_full Asserted

Figure 2:UI Command Timing with app_full Asserted

Available commands on the app_cmd port are as follows:

Figure-3 Commands for app_cmd[2:0]

Figure 3:Commands for app_cmd[2:0]

Note that Refresh is not a user command. The core performs auto-refresh to the memory at regular intervals. For more information on auto-refresh, see (Xilinx Answer 34371).

For more details on sending specific commands and the addressing scheme see the following:

(Xilinx Answer 34763) - Performing Reads
(Xilinx Answer 34677) - Performing Writes
(Xilinx Answer 34779) - Addressing
(Xilinx Answer 34780) - Masking Data
(Xilinx Answer 35091) - When app_rdy is not asserted
(Xilinx Answer 34941) - Available DDR commands
(Xilinx Answer 35410) - How many commands can be stored?

For additional information, please refer to the DDR2/DDR3 Memory Interface Solution > Interfacing to the Core section in the Virtex-6 FPGA Memory Interface Solutions User Guide (UG406) and the 7 Series FPGAs Memory Interface Solutions User Guide (AXI) (UG586).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34320 MIG 7 Series and Virtex-6 DDR2/DDR3 - Usage of User Design N/A N/A
34790 MIG Virtex-6 and 7 Series DDR2/DDR3 - User Interface N/A N/A

Child Answer Records

Associated Answer Records

AR# 33698
Date 02/22/2013
Status Active
Type Solution Center
Devices More Less