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AR# 33740

11.3 Spartan-6/Virtex-6 FPGA MAP - IODELAYs are being auto-inserted for some paths in ISE version 11.3 but were not in ISE 11.2.


My design was working in ISE version 11.2, but does not work in 11.3.

I have located the issue to an input FF in an ILOGIC component.

The data path has an IODELAY inserted in it, whereas this did not happen in 11.2.
Why has this changed?


A change was made in ISE software version 11.3 so that IODELAYs were incorrectly inserted on the data path of input FFs when clocked from a DCM-->BUFG-->FLOP clock path.

This change is removed from ISE software version 11.4.

In ISE 11.3 , the IODELAY insertion can be prevented by putting an IODELAY=NONE attribute on either the pad or pad net.

Example UCF syntax to override auto-insertion of IODELAY components is below:


NET "pad_net_name" IOBDELAY=NONE;

AR# 33740
Date 07/29/2014
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Virtex-6 CXT
  • More
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
  • ISE Design Suite - 11.3
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
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