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AR# 33741

MIG v3.2, v3.3, Virtex-4/-5 FPGA DDR/DDR2 - The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column

Description

The timing spreadsheet provided to calculate timing margin before and after DQS incorrectly only accounts for Tstaphaoffset in the "Before DQS" column.

Solution

The timing parameter for the PLL static offset, Tstaphaoffset, should be accounted for in both the Before and After DQS column of the spreadsheet write_data_timing.xls. In MIG 3.2, this parameter is only accounted for in the "Before DQS" column, while the "After DQS" column lists it is contribution as 0ps.

This issue is to be fixed in the 12.1 software release. For now, you must manually update the spreadsheet to use the same value listed in the "Before DQS" column in the "After DQS" column for the parameter Tstaphaoffset.

AR# 33741
Date Created 11/04/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
IP
  • MIG