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MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - Read Modify Write command fails when using Data Mask to mask individual bytes
The MIG v3.3 Virtex-6 FPGA DDR2/DDR3 designs support Read Modify Write commands.
When a read-modify-write is performed in conjunction with a partial data mask, the modified data is not written to the memory.
This is a known issue with MIG v3.3 which affects both simulation and hardware.
To avoid this issue, read-modify-write commands should not be performed with a partial data mask.
This issue is scheduled to be resolved in the next version of MIG (released with ISE Design Suite 12.1).
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- Virtex-6 CXT
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