AR# 33804


MIG v3.3, Virtex-6 FPGA, DDR2 - Timing parameter tRC min is violated if CAS Latency (CL) equals 4 with 2T timing


The MIG v3.3 Virtex-6 FPGA DDR2 designs violate the tRC timing parameter (Activate to Activate time) for a design with CAS Latency (CL) = 4 using 2T timing.


This issue affects both simulation and hardware.

To work around this issue, a CL of 2 can be used.

This issue is resolved in MIG v3.4, which was released with ISE Design Suite 12.1.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33706 MIG v3.3 - Release Notes and Known Issues for ISE Design Suite 11.4 N/A N/A
AR# 33804
Date 08/20/2014
Status Active
Type General Article
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