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AR# 33807

MIG v3.3, Virtex-6 FPGA, DDR2/DDR3 - The VHDL traffic generator hangs after a few reads for designs with a Burst Length of 4

Description

The MIG v3.3 DDR2/DDR3 designs include a traffic generator within the example_design output. The VHDL version of this traffic generator hangs after a few reads for designs with a Burst Length of 4.

Solution

This issue affects both simulation and hardware, and only affects the VHDL example design. The user design does not contain the example traffic generator and is not affected by this issue. To see a working simulation using the traffic generator, use the Verilog example design.

This issue is resolved in MIG v3.4which wasreleased with ISE Design Suite 12.1.

AR# 33807
Date Created 11/14/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG