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AR# 33808

SPI-3 Link Layer v7.1 - "ERROR:Pack:1653 - At least one timing constraint is impossible to meet.."

Description

The following Map error may occur even after modifying the DCM Phase Shift value as per (Xilinx Answer 34527) in ISE 11.4 or earlier:

"ERROR:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint."

Solution

This issue has been fixed in ISE design tools 11.5.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
32651 Spartan-6 - ISE Software 11 Update Known Issues related to Spartan-6 FPGA N/A N/A
AR# 33808
Date Created 11/12/2009
Last Updated 05/19/2012
Status Archive
Type Known Issues