General Description: Design using Viewlogic targeting 4010E and brought into M1.4. In MAP, during Optimizing, the following error occurs: FATAL_ERROR:x4ema:x4emaclb.c:663:1.44:5.2 - Flop in Y found. Process will terminate. Please call Xilinx support. This design ran through fine in Xact 6.0.1. The error still occurs with the latest core_nt patch.
Resolution 1: The workaround is to run MAP with the "-l" option. This option is available in the Design Manager GUI under Implement Options. Click on Edit Template for Implentation and De-Select Replicate Logic to Allow Logic Level Reduction. This Fatal Error was caused because the trimming step in logic replication has encoutered a fully constrained and packed CLB.
A fix for this error is included in the current M1.4 Core Applications patch available from the Xilinx Download Area: