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AR# 33816

11.1 EDK, MPMC v5.01.a - MPMC integrated MIG flow does not modify all UCF names for Virtex-4 and Spartan-3 FPGA

Description

When using the integrated MIG GUI in MPMC with a Virtex-4 FPGA DDRor Spartan-3FPGA DDR/DDR2 design, errors occur in NGDBuild (Translate) or some I/O are placed in random locations.

How do I resolve this issue?

Solution

To work around this problem, edit the MIG generated UCF (<EDK Project DIR>/__xps/mig/gui/<MPMC Instance Name>/user_design/par/<MPMC Instance Name>.ucf) to vectorize the offending signals; typically, cke, cs_n, and odt.

For example, change the following lines from:

NET "cntrl0_ddr_cke" IOSTANDARD = SSTL2_II;

NET "cntrl0_ddr_cs_n" IOSTANDARD = SSTL2_II;

NET "cntrl0_ddr2_odt" IOSTANDARD = SSTL18_II; #DDR2 only

NET "cntrl0_ddr_cke" LOC = "W22" ;

NET "cntrl0_ddr_cs_n" LOC = "W23" ;

NET "cntrl0_ddr2_odt"LOC = "U20" ; #DDR2 only

to:

NET "cntrl0_ddr_cke[*]" IOSTANDARD = SSTL2_II;

NET "cntrl0_ddr_cs_n[*]" IOSTANDARD = SSTL2_II;

NET "cntrl0_ddr2_odt[*]" IOSTANDARD = SSTL18_II; #DDR2 only

NET "cntrl0_ddr_cke[0]" LOC = "W22" ;

NET "cntrl0_ddr_cs_n[0]" LOC = "W23" ;

NET "cntrl0_ddr2_odt[0]"LOC = "U20" ; #DDR2 only

After making the modifications, Clean Hardware and Generate Netlist in XPS to include the UCF changes.

This issue is scheduled to be fixed in MPMC v5.05.a and later, to be released in EDK 12.1.

AR# 33816
Date Created 11/12/2009
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 SX
  • More
  • Spartan-3
  • Spartan-3 XA
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Less
Tools
  • EDK - 10.1 sp2
  • EDK - 10.1
  • EDK - 10.1 sp1
  • More
  • EDK - 10.1 sp3
  • EDK - 11.1
  • EDK - 11.2
  • Less
IP
  • Multi-Port Memory Controller (MPMC)