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AR# 33823

11.x ChipScope Pro Analyzer - qvirtex5 - "ERROR:Pack:2811 - Directed packing was unable to obey the user design"

Description

Keywords: LogiCORE, CoreGENERATOR, VIO, ILA, ICON, map, ISE

When I generate a design targeting a QVirtex-5 FPGA part that includes ChipScope analyzer cores generated by Coregen, I see multiple errors at Map. The messages state -

ERROR:Pack:2811 - Directed packing was unable to obey the user design
constraints
(MACRONAME=i_ila/U0/I_NO_D.U_ILA/U_G1.U_CAPCTRL_U_CAP_ADDRGEN_U_WCNT_HCMP_I_S
RL16.U_GAND_SRL16_MSET, RLOC=X0Y0) which requires the combination of the
symbols listed below to be packed into a single SLICEM component.

These are ChipScope analyzer related messages. How do I work around this issue?

Solution

There are two work-arounds:
1) Use the ChipScope Inserter for ILA and ATC2 cores.
2) Generate cores targeting Virtex-5 FPGA and use the resulting netlist on the qvirtex5 target.

This issue will be resolved in ChipScope Pro Analyzer 12.1
AR# 33823
Date Created 11/13/2009
Last Updated 11/12/2009
Status Active
Type General Article