You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
MIG v3.3, Virtex-6 FPGA DDR3 DIMM - MIG does not allocate two sets of CK/CK#, CS and ODT for data widths using two DIMMs
The MIG v3.3 Virtex-6 FPGA DDR3 design should allocate two sets of the following signals when designs with data widths using two DIMMs are generated (i.e., 144-bit designs using two 72-bit DIMMs).
These signals should be replicated for each DIMM, but instead, only one set of these control signals is generated.
This issue is scheduled to be resolved in MIG v3.4, which is to be released with ISE Design Suite 12.1.
Was this Answer Record helpful?
Linked Answer Records
Master Answer Records
- Virtex-6 CXT
- Virtex-6 HXT
- Virtex-6 LX
- Virtex-6 LXT
- Virtex-6 SXT