AR# 33832


MIG v3.3, Virtex-6 FPGA DDR3 DIMM - MIG does not allocate two sets of CK/CK#, CS and ODT for data widths using two DIMMs


The MIG v3.3 Virtex-6 FPGA DDR3 design should allocate two sets of the following signals when designs with data widths using two DIMMs are generated (i.e., 144-bit designs using two 72-bit DIMMs).
  • CK/CK#
  • CS
  • ODT

These signals should be replicated for each DIMM, but instead, only one set of these control signals is generated.


This issue is scheduled to be resolved in MIG v3.4, which is to be released with ISE Design Suite 12.1.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
33706 MIG v3.3 - Release Notes and Known Issues for ISE Design Suite 11.4 N/A N/A
AR# 33832
Date 08/20/2014
Status Active
Type General Article
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