In the Spartan-6 FPGA GTP Transceivers, User Guide (UG386), Table 3-1: FPGA TX Interface Ports claims that:
"If the PLL is shared between both GTP transceivers, then INTDATAWIDTH0 must equal INTDATAWIDTH1>."
The intention of this note is to cover general cases where both lanes within a single DUAL are being used. However, there could be some particular cases where INTDATAWIDTH1 can be different from INTDATAWIDTH0, this can happen especially when one of the two GTP in the DUAL is not used.
As an example, assume that only one GTP (GTP1) is used in the DUAL, the 8B10B codec is enabled, and the ratio between the datarate and the reference clock frequency must be 8.
A feedback divider of 4 is needed to achieve the correct datarate from the reference clock oscillator frequency, but an INTDATAWIDTH1 of 5 is needed because the 8B10B encoder is used in GTP1.
In this particular case, the REFCLK can be multiplied by 4 in GTP0 PLL (INTDATAWITH0=0) and then to shared with the GTP1. This allows a higher flexibility degree.