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AR# 33887

LogiCORE IP Display Port v1.1 - Why is my HSYNC timing incorrect when using the dual pixel mode for some frequencies?

Description

Why is my HSYNC timing incorrect when using the dual pixel mode for some frequencies?

Solution

This is a known bug in the Display Port v1.1. 

 

Please see (Xilinx Answer 33258) for a detailed list of LogiCORE Display Port Release Notes and Known Issues.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
33258 LogiCORE IP DisplayPort - Release Notes and Known Issues N/A N/A
AR# 33887
Date Created 11/30/2009
Last Updated 05/23/2014
Status Archive
Type General Article