You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
M1 docs., library guide,X74_168: Fig. 12.12, shown cascading counter is wrong.
Keywords: carry, logic, cascade, x74_168, 74168
Fig. 12-12 in M1 documentation CD shows how to cascade x74_168
with carry lookahead.
The figure is wrong.
ENP of the first stage and ENT of the second
stage should be connected to GND.
The connection shown is to VCC. With this connection, the
counter will not count up/down.
Change the ENP of the first stage and ENT of the second
stage connection to GND.
Was this Answer Record helpful?