I placed a TPSYNC on a LUT PIN and then created FROM:TO constraints going FROM and TO this PIN. I am not seeing the analysis done correctly.
In my PR design I sometimes see static routes to Partition PINs analyzed and in different configuration. I don't see the same static route analyzed with the same constraints. Why?
If a TPSYNC is placed on a LUT PIN and the LUT drives a FF that is in the same slice, then the analysis is performed correctly. However, if the LUT drives a FF that is in a different slice the analysis is not performed.
We are currently investigating this issue. This issue is scheduled to be fixed in a future version of ISE.