AR# 33920

11.x ChipScope Pro tool - IBERT - Virtex-6 FPGA - Clock Pattern on Reflck is incorrect


When I probe the Refclk on my Virtex-6 FPGA IBERT design, I do not see the clock frequency I expect. What is the issue here?


This issue will occur when you use the 16-bit data width. To work around it, regenerate for 20-bit data width. If you require further assistance with this, please open an online WebCase with Xilinx Customer Support:

AR# 33920
Date 12/15/2012
Status Archive
Type General Article