We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 33925

Virtex-5 GTX RocketIO Wizard v1.6 - "Warning: At time 55134250, RDEN on AFIFO36_INTERNAL instance testbench.DUT.xaui_block.rocketio_wrapper_i.tile1_gtp0_cc_2b_1skp_i.cc_fifo.INT_FIFO.genbl..."


If I simulate a design that utilizes the external Clock Correction Module generated by the Virtex-5 FPGA RocketIO Wizard, the following warning appears: 


"Warning: At time 55134250, RDEN on AFIFO36_INTERNAL instance testbench.DUT.xaui_block.rocketio_wrapper_i.tile1_gtp0_cc_2b_1skp_i.cc_fifo.INT_FIFO.genbl 

k1 is high when RST is high. RDEN should be low during reset."


This warning can safely be ignored without impacting the functionality of the simulation. This is not a concern for hardware implementations.

AR# 33925
Date 05/23/2014
Status Archive
Type General Article
Page Bookmarked