When dynamic phase shift is selected as a feature in the Virtex-6 FPGA Clocking Wizard v1.4, the wizard does not set the attribute CLKOUTn_USE_FINE_PS to TRUE. The resulting wizard output does not have dynamic phase shift enabled.
This issue will be resolved in the next release of software.
In the meantime, use the override mode on page 4 of the Clocking Wizard to enable CLKOUTn_USE_FINE_PS for each output that needs the dynamic phase shift feature. Please note that the MMCM attributes edited in override mode match up to the MMCM outputs. The MMCM outputs correspond to the Clock Wizard ports as follows (where Clock Wizard Port <= MMCM output): CLK_OUT1 <= CLKOUT0 CLK_OUT2 <= CLKOUT1 CLK_OUT3 <= CLKOUT2 CLK_OUT4 <= CLKOUT3 CLK_OUT5 <= CLKOUT4 CLK_OUT6 <= CLKOUT5 CLK_OUT7 <= CLKOUT6 CLKFB_OUT <= CLKFBOUT