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AR# 33943

ChipScope IBERT, Virtex-5 - IBERT core generation fails at the Map stage


IBERT core generation fails at the Map stage. When I check the ".mrp" report in the implementation directory, the following message appears:

"ERROR:Pack:2811 - Directed packing was unable to obey the user design constraints (LOC=***) which requires the combination of the symbols listed below to be packed into a single IPAD component."

How do I work around this issue?


This issue occurs if you use a clock location for an MGT reference clock. Check that you have selected a valid pin location for your input clock. Regenerate with a valid clock location.

AR# 33943
Date 12/15/2012
Status Active
Type General Article
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