In Spartan-6 FPGA, when MPMC is used with Clock Generator v3.02.a to access LPDDR memory, the following message occurs:
The bus clock <83.000000> for the MPMC is invalid. The MPMC runs at a ratio of 1:1 or 2:1 of the bus. The MPMC clock speed must be from <-0.000001> to <-0.000001> MHz.
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How do I resolve this issue?
Clock Generator currently does not support LPDDR memory.
To work around this issue, consider editing the Clock Generator parameters manually through the MHS file. Alternatively, it might be possible to set the MPMC to use a memory type other than LPDDR, use the Clock Generator GUI as necessary, and then set the MPMC back to use LPDDR.
Clock Generator is scheduled to support LPDDR memory starting in EDK 12.1.