The tx_sync module generated by the GTP RocketIO Wizard does not assert TXPMASETPHASE for the correct number of cycles when it is being used for only TX skew reduction. This answer record discusses what modifications can be made to the tx_sync module to align with the guidelines in UG196, the Virtex-5 FPGA GTP RocketIO User's Guide.
1) Expand sync_counter_r to be [16:0]
2) Depending on the value of PLL_TXDIVSEL_COMM_OUT, sync_count_complete_r needs to be connected to one of three bits in the counter register:
1: sync_count_complete_r = sync_counter_r
2: sync_count_complete_r = sync_counter_r
4: sync_count_complete_r = sync_counter_r