ISE Design Suite 11.4.1 is alimited release thatis for customers who have received Production6VLX240T silicon only. If you have further questions, please contactTechnical Support. Critical: You must rerun your design through the implementation tools after installing ISE Design Suite 11.4.1.
Certain IP products may error during implementation due to new requirements on the Virtex-6 FPGA MMCM attribute settings. See Xilinx Answer 33849 which is also listed below for more information.
Please note that the 6VLX240T speeds filesincluded in this update have been verified against production silicon and are now labeled "PRODUCTION." However, full hardware validationof IP coresis NOT available for ISE Design Tools 11.4.1. If you experience issues with IP Cores, please reference theKnown Issues section of this Answer Record.Bug fixes for most issueswill be in a future ISE Design Suite update(currently scheduled for March2010).
(Xilinx Answer 33849) Virtex-6 FPGA MMCM - New Requirements for DRP/Phase Shift, VCO minimum frequency, and CLKFBOUT_MULT_F values
(Xilinx Answer 32929) Virtex-6 - 11.x Software Known Issues related to the Virtex-6 FPGA
(Xilinx Answer 34146) Virtex-6 Integrated Block Wrapper v1.4 for PCI Express - Timing Analysis Fails "Pin to Pin Skew Constraint" after installing 11.4.1
(Xilinx Answer 34181) 11.4.1 - System Generator for DSP - What are the known issues in using System Generator 11.4 with ISE 11.4.1?