AR# 3402


FPGA Express 1.2/2.0/F1.5 : clock buffer not inserted if clock net sources RAMs or Black Boxes


Keywords: FPGA Express, COREGen, black box, clock buffer, RAM, ROM, Virtex, Block RAM

Urgency: Standard

General Description:
FPGA Express has the ability to infer clock buffers for appropriate signals. However, for black box and RAM/ROM instantiations, Express is unable to determine which pin, if any, deserves the use of a clock buffer, even if that signal also sources clock pins on inferred flip-flops.

The resulting netlist will have an IBUF inserted for the black boxes and instantiated RAM/ROM. If the signal is also used to clock inferred flip-flops, the IBUF will be inserted in parallel to the clock buffer. Although this is not illegal in the Xilinx architectures, it is not an optimal use of resources.

In the Virtex flow with Foundation Express 1.5, this situation can happen when the COREGen tool is used to make a large block of Block RAM. The COREGen block RAM macro is a black-box.



This behavior has been fixed for all families (except Virtex) in Express 2.1. If a clock net sources both inferred logic and a black box, a clock buffer will be used for all these destinations. If a clock buffer only sources black boxes, then the clock buffer will still have to be instantiated.

If you are using a Virtex device, you must use Resolution #2, and you must select a BUFGP (a BUFG will not work).


A work-around is to instantiate the clock buffer on the clock signal. The following are examples of a global buffer instantiation in VHDL and Verilog.

--VHDL Example:

library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity Multiplier is

port ( Cin : in std_logic_vector(13 downto 0);
Din : in std_logic_vector(12 downto 0);
CLK : in std_logic;
Result : out std_logic_vector (26 downto 0));

end multiplier;

architecture Mult_arch of Multiplier is

signal CLK_OUT : std_logic;

component BUFG port( I : in std_logic;
O : out std_logic);
end component;

component mul14x13 port (
A: IN std_logic_VECTOR(13 downto 0);
B: IN std_logic_VECTOR(12 downto 0);
PROD: OUT std_logic_VECTOR(26 downto 0);
C: IN std_logic);
end component;

U1: BUFG port map (I=>CLK, O=>CLK_OUT);

U2: mul14x13 port map (A=>Cin, B=>Din, PROD=>Result, C=>CLK_OUT);
end mult_arch;

//Verilog Example:

module multiplier (Cin, Din, CLK, Result);

input [13:0] Cin;
input [12:0] Din;
input CLK;
output [26:0] Result;

reg [26:0] Result;


mul14x13 U2 (.A(Cin), .B(Din), .PROD(Result), .C(CLK_OUT));

AR# 3402
Date 06/21/2001
Status Archive
Type General Article
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