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AR# 34032

Config - What is the relationship between the TCK output and clock input frequencies for XAPP424?


What is the clock relationship between the input design frequency and the effective output JTAG TCK frequency?

Formore FPGA Device Specific Issues and other Configuration Related Articles, see(Xilinx Answer 34104).


The ratio for the input (CLK) and output (TCK) frequencies is 14:1 during a shift; it takes 14 input clocks to complete a TCK data shift operation. This is due to the state machine that is implemented as part of the System ACE Player IP provided in(XAPP424).

As an example, if a customer needs a 10 MHz TCK on the JTAG chain, the input CLK frequency should be 140 MHz.
AR# 34032
Date 12/15/2012
Status Active
Type General Article
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