"> AR# 34038: 11.3 Virtex-4 PAR - PAR crashes at the end of processing

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AR# 34038

11.3 Virtex-4 PAR - PAR crashes at the end of processing

Description

When I run my Virtex-4 FPGA design on a Windows Vista machine with the Timing Driven Map option turned off, PAR appears to run to completion successfully, but then posts one of the following pop-up errors at the end of processing. Is this a known problem?



On a Windows XP machine, the error is as follows:


The messages printed in theISE console are as follows:


All signals are completely routed.

Total REAL time to PAR completion: 3 mins 53 secs
Total CPU time to PAR completion: 3 mins 42 secs
Peak Memory Usage: 436 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 2

Writing design to file tr_fpga_top_v4sx35f668.ncd

This application has requested the Runtime to terminate it in an unusual way.

Please contact the application's support team for more information.

Process "Place & Route" failed

Solution

This problem only occurs withVirtex-4 FPGA designs using the non-timing driven flow (placement performed by PAR). Towork aroundthis issue,use the timing driven MAP flow (placement performed by MAP) which has the added value of improving QOR.

Due to limited exposure and an easy work-around, no fix is scheduled for this issue.

AR# 34038
Date Created 01/13/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
Tools
  • ISE Design Suite - 11.3