When I run a simulation using code that instantiates Xilinx primitives, the following error occurs:
# ** Error: (vsim-19) Failed to access library 'unisims_ver' at "unisims_ver".
# No such file or directory. (errno = ENOENT)
# ** Error: (vopt-19) Failed to access library 'D:\Xilinx\11.1\ISE\verilog\mti_se\6.5b\nt/unisims_ver' at "D:\Xilinx\11.1\ISE\verilog\mti_se\6.5b\nt/unisims_ver".
# Permission denied. (errno = EACCES)
How can I resolve these issues?
In order to simulate designs with instantiated behavioral or timing primitives, ModelSim requires that the Xilinx libraries are referenced in the "modelsim.ini".Follow these directions to resolve the issues above:
Refer to the Synthesis and Simulation User Guide in the Documentation Centerfor more information about setting up your simulator environment for Xilinx designs.
If the information in this Answer Record does not address the simulation errors, please contact Xilinx Technical Support using the Contact Supportmethods.