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AR# 34084

Serial RapidIO v5.4 - MMCM values incorrect for certain core settings in Virtex-6 devices

Description

In v5.4 of the Serial RapidIO Core, the settings used for the MMCM cause the VCO frequency to fall outside of the supported range which might result in excessive jitter and clocking problems.

This is fixed in v5.4 Rev1 of the core available in ISE 11.5.

Solution

To work around this issue, upgrade to v5.4 Rev1 of the core and ISE 11.5, or perform the following:

Four attributes need to be changed in the MMCM instantiation which can be found inside the example_design/<core_name>_clk.v(hd) file. The four attributes are: DIVCLK_DIVIDE, CLKFBOUT_MULT_F, CLKOUT0_DIVIDE_F, and CLKOUT1_DIVIDE. The new correct values depend on the Transfer Frequency and Reference Clock Frequency being used. The table below lists the current incorrect values in v5.4 of the core and the correct values that the attributes should be modified to (marked in red).


Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A
AR# 34084
Date Created 01/20/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Serial RapidIO