UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34094

MIG v3.3, Virtex-6 FPGA DDR2/DDR3/QDRII+/RLDRAM - MMCM CLKFBOUT_MULT_F = 2,3,4 not valid, manual modification required

Description

When using an MMCM in Virtex-6 FPGA, setting the CLKFBOUT_MULT_F to 2, 3, and 4 might cause the MMCM not to lock. MIG determines the value of CLKFBOUT_MULT_F parameter in order to ensure that the internal VCO frequency of MMCMs used in the design are as high as possible. Having a higher VCO frequency reduces jitter on the output clocks.

DDR2/DDR3
In the MIG DDR2/DDR3 design, there are two MMCMs that could be affected by this issue. One is located in module infrastructure.v/.vhd and the other in phy_rdclk_gen.v/.vh.

QDRII+/RLDRAM
In the MIG QDRII+ and RLDRAM designs there is one MMCM that could be affected by this issue. The MMCM is located in the module infrastructure.v/.vhd.

The following tables show the memory clock period ranges over which manual modification will need to be applied to the parameters of one or both of the MMCMs in order to avoid the use of CLKFBOUT_MULT_F = 2/3/4. Note that the period ranges that affect each MMCM are different, and there may be some cases where parameter modification must be applied to one MMCM but not the other.

The setting of CLKFBOUT_MULT_F = 4is generated by MIG for the MMCM in infrastructure.v/.vhd for the following frequencies (DDR2/DDR3/QDRII+/RLDRAM):
FPGA Speed Grade From (ps) To (ps) From (ps) To (ps)
-1 3334 4166
-2 1875 1999 2778 3472
-3 2500 3124

Note that for the -2 speed grade, there are two frequency ranges over which the CLKFBOUT_MULT_Fis set to 4 by MIG.

The setting of CLKFBOUT_MULT_F = 4is used for the MMCM in phy_rdclk_gen.v/.vhd for the following frequencies (DDR2/DDR3):
FPGA Speed Grade From (ps) To (ps) From (ps) To (ps)
-1 3336 4169
-2 3336 4169 1875 1999
-3 3336 4169 1875 1999

Note that for the -2 and -3 speed grades, there are two frequency ranges over which the CLKFBOUT_MULT_Fis set to 4 by MIG.

The setting of CLKFBOUT_MULT_F = 3 is generated by MIG for the MMCM in infrastructure.v/.vhd for the following frequencies (DDR2/DDR3/QDRII+/RDLRAM):
FPGA Speed Grade From (ps) To (ps)
-1 2500 3333
-2 2084 2777
-3 1875 2499


The setting of CLKFBOUT_MULT_F = 3 is used for the MMCM in phy_rdclk_gen.v/.vhd for the following frequencies (DDR2/DDR3):
FPGA Speed Grade From (ps) To (ps) From (ps) To (ps)
-1 2502 3335
-2 2502 3335 2085 2500
-3 2502 3335 2085 2500



The setting of CLKFBOUT_MULT_F = 2 is generated by MIG for the MMCM in infrastructure.v/.vhd for the following frequencies (DDR2/DDR3/QDRII+/RLDRAM):
FPGA Speed Grade From (ps) To (ps)
-1 2223
2499
-2 2000 2083
-3 NA NA


The setting of CLKFBOUT_MULT_F = 2 is used for the MMCM in phy_rdclk_gen.v/.vhd for the following frequencies (DDR2/DDR3):
FPGA Speed Grade From (ps) To (ps)
-1 2501 2501
-2 2000 2084
-3 2000 2084


The ISE 11.4 design tools do not generate an error and issues might be seen in hardware. In ISE 11.5 the following MAP error will occur due to a new DRC:

ERROR:LIT:586 - MMCM_ADV symbol "physical_group_u_infrastructure/clk_pll/u_infrastructure/u_mmcm_adv" has attribute CLKFBOUT_MULT_F set to a value that is outside the valid range of 5 to 64.


Note that there is a related issue with the MMCM where certain combinations of the MMCM counter settings, phase shift, and all settings of the variable fine phase shift might cause the CLKOUTn phase shift to show up incorrectly in hardware.This is documented in (Xilinx Answer 33849).

Solution


To work around this issue, users need to manually modify the MMCM parameters to ensure the CLKFBMULT_OUT parameter is not set to 2/3/4, but the VCO frequency is still as high as possible.

Work-around Steps forinfrastructure.v:
Note: Only perform these stepsif the frequency of operation falls in the range where CLKFBOUT_MULT_F is normally set to 2/3/4
Note: Example is shown for Verilog only. VHDL parameters are named the same and should follow the same steps.



1. Open the top-level MIG rtl module. For the Example Design, this will be example_top.v/.vhd. For the User Design, this will be core_name.v/.vhd.

2. Find the following parameters in the module declaration:

parameter CLKFBOUT_MULT_F = 4,
// write PLL VCO multiplier.
parameter DIVCLK_DIVIDE = 2,
// write PLL VCO divisor.
parameter CLKOUT_DIVIDE = 2,
// VCO output divisor for fast (memory) clocks.

3. Modify the parameters to ensure the M (CLKFBOUT_MULT_F) to D (DIVCLK_DIVIDE) relationship is maintained. The CLKOUT_DIVIDE parameter should not be modified.
  • For MIG generated CLKFBOUT_MULT_F values of 2, M (CLKFBOUT_MULT_F) and D (DIVCLK_DIVIDE) should be multiplied by 3.
  • For MIG generated CLKFBOUT_MULT_F values of 3 or 4, M (CLKFBOUT_MULT_F) and D (DIVCLK_DIVIDE) should be multiplied by 2.


Work-around Steps for phy_rdclk_gen.v:
Note: Only perform these stepsif the frequency of operation falls in the range where CLKFBOUT_MULT_F is normally set to 2/3/4
Note: Example is shown for Verilog only. VHDL parameters are named the same and should follow the same steps.



1. Open the module phy_rdclk_gen.v/.vhd

2. Locate the instantiation of the MMCM "u_mmcm_clk_base" and the following parameters (Verilog syntax shown):
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT),

3.Increase the parameters:
  • For MIG generated CLKFBOUT_MULT_F values of 2, increase both of these parameters by a factor of 3:
.DIVCLK_DIVIDE (3 * DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (3 * CLKFBOUT_MULT),
  • For MIG generated CLKFBOUT_MULT_F values of 3 and 4, increase both of these parameters by a factor of 2:
.DIVCLK_DIVIDE (2 * DIVCLK_DIVIDE),
.CLKFBOUT_MULT_F (2 * CLKFBOUT_MULT),


MIG v3.4, available with ISE 12.1, will automatically set the correct M and D values to avoid the 2, 3, and 4 settings.



It is possible that the multiplier in the top level and the phy_rdclk_gen.v may not match up, if this is the case, you can multiply them by their respective values. This is not a problem as the ratio between the two files will still be 1 to 1.



For example, you may multiply by 3 in the top level and by 2 in the phy_rdclk_gen.v.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
34019 ISE Design Suite 11.4.1 - Known Issues for Virtex-6 FPGA Service Pack N/A N/A

Associated Answer Records

AR# 34094
Date Created 01/11/2010
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Less
IP
  • MIG