AR# 34142

Spartan-6 - What is the best way to find which I/Os are related to a specific BUFIO2 site?


The Spartan-6 FPGA Clocking Resources User Guide (UG382) refers to the BUFIO2 Clocking Region information in the Spartan-6 FPGA Packaging and Pinout Specification (UG385), but the information is not available in this document.


The BUFIO2 Clocking Region information is scheduled to be added to a future release of the Spartan-6 FPGA Packaging and Pinout Specification (UG385). Please note that the Clocking Region names in the documentation are going to change from "A, B, C, D, E, F, G, H" to "TL, TR, RT, RB, BR, BL, LB, LT". TL = Top Left, or the left half of the top edge, and matches the constraint syntax that can be used on the pins to force them to a particular BUFIO2 Clocking Region. Both UG382 and UG385 are expected to be updated by the end of February 2010. The current Spartan-6 FPGA ASCII package files on are also going to be updated with the correct BUFIO2 information (this is expected to be done by early May 2010). To request an advance copy of an ASCII package file, contact Xilinx Support with the part/package combination of interest.

The package files are going to be changed to what is shown below. As you can see, all of these pins are located in the TL BUFIO2 Clock Region (top left of the device):

Pin Bank BUFIO2 Pin Description
C5 0 TL IO_L2P_0
A5 0 TL IO_L2N_0
D6 0 TL IO_L3P_0
C6 0 TL IO_L3N_0
B6 0 TL IO_L4P_0
A6 0 TL IO_L4N_0
C7 0 TL IO_L5P_0
A7 0 TL IO_L5N_0
B8 0 TL IO_L6P_0
A8 0 TL IO_L6N_0
D7 0 TL IO_L7P_0
C8 0 TL IO_L7N_0
C9 0 TL IO_L8P_0

It is good design practice to use the fewest amount of clock buffer resources as possible.You can accomplish this by staying in one BUFIO2 clock region (half bank). The software tools can assist you when pinning out a design if you use the LOC constraints as follows (which will LOC to a region and not a specific pin):

TL - Top Left
TR- Top Right
RT- Right Side Top
RB- Right Side Bottom
BR- Bottom Right
BL- Bottom Left
LB- Left Side Bottom
LT- Left Side Top

Following is how it can be entered in the UCF:

Inst CLOCK1 Loc = TL;
Inst Data[0] Loc = TL;
Inst Data[1] Loc = TL;
Inst Data[2] Loc = TL;
Inst Data[3] Loc = TL;

Using the above constraint allows the designer to ensure that all related I/Os and Clocks are located in the correct half of a bank (BUFIO2 clock region) during the first implementation run. After the first run, the constraints can then be fine-tuned based on the initial placement given by the tools.

More information on this can be found in the Spartan-6 FPGA SelectIO Resources User Guide (UG381):

AR# 34142
Date 12/15/2012
Status Active
Type General Article