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AR# 34188

PlanAhead - Error on placing valid LOC (e.g. clock pin on a GCLK0) for an Automotive Spartan-3A/E device

Description

When I attempt to place a clock pin on a valid site (for example: GCLK0 Pin) using pre-synthesis pin planning, I get a warning and error similar to the following:

WARN: [HD-UCFReader 12] Cannot place terminal 'CLK_IN' legally at site P80, found on line 12, Illegal to place instance Clock_divider_i/IBUFG_i on site P80, using FORCE placement mode
ERROR: [HD-UCFReader 25] Cannot loc terminal 'CLK_IN' at site P80 found on line 12, Illegal to place instance Clock_divider_i/IBUFG_i on site P80"

This error seems to occur for Automotive Spartan-3A/E devices only. 

I am able to perform this task on other Spartan-3A and Spartan-3E devices. 

Why does this happen?

Applying UCF constraints post synthesis works without issue.

Solution

This is a known issue in the PlanAhead software where it does not allow the placement of clock pins on GCLK pins for Automotive Spartan-3A/E devices.

To work around the issue, use post synthesis I/O planning or apply them directly through the UCF constraints file.

AR# 34188
Date Created 01/20/2010
Last Updated 01/30/2015
Status Active
Type Known Issues
Tools
  • PlanAhead