The Wizard included with 11.5 will update the many attributes necessary for correct operation in production silicon. The values for production silicon are as follows, with the design specific selections on the left and the dependant attributes on the right:
1. This table does not include values for TX/RXPLL_DIVSEL_FB = 1 as those values are not supported. When porting a design from ES to production, DIVSEL_REF can be used to pre-divide in input clock, allowing the use of PLL_DIVSEL_FB = 2 to accomplish the same PLL rate.
For information on which versions of the Virtex-6 Transceiver Wizard support ES and Production silicon, please refer to the following table:
Virtex-6 GTX Wizard
Version of wizards included in CORE Generator release
v1.4 Rev 1
Virtex-6 FPGA CES Silicon