UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34191

Virtex-6 FPGA GTX Transceiver Wizard - Attribute updates for production silicon

Description

The Virtex-6 FPGA GTX Transceiver Wizard v1.4 rev1, included with ISE Design Suite 11.5, has attribute settings that have been optimized for production silicon. The output from earlier versions of the Wizard need to be replaced or updated with new attribute settings when used with production silicon. This Answer Record discusses what changes need to be made.

Solution

The Wizard included with 11.5 will update the many attributes necessary for correct operation in production silicon. The values for production silicon are as follows, with the design specific selections on the left and the dependant attributes on the right:



NOTES:

1. This table does not include values for TX/RXPLL_DIVSEL_FB = 1 as those values are not supported. When porting a design from ES to production, DIVSEL_REF can be used to pre-divide in input clock, allowing the use of PLL_DIVSEL_FB = 2 to accomplish the same PLL rate.

For information on which versions of the Virtex-6 Transceiver Wizard support ES and Production silicon, please refer to the following table:

Virtex-6 GTX Wizard

ISE 11.2

ISE 11.3

ISE 11.4

ISE 11.5

ISE 12.1

Version of wizards included in CORE Generator release

V1.2

V1.3

V1.2

V1.4

V1.3

V1.4 Rev1

V1.3

V1.5

V1.4 Rev1

Virtex-6 FPGA
Production Silicon

NA

NA

NA

v1.4 Rev 1

v1.5

Virtex-6 FPGA CES Silicon

v1.2

v1.3

v1.4

v1.3

No support



AR# 34191
Date Created 02/08/2010
Last Updated 06/01/2010
Status Active
Type General Article
Devices
  • Virtex-6 CXT
  • Virtex-6 LXT
  • Virtex-6 SXT
IP
  • Virtex-6 GTX Transceiver Wizard