When I applyresets to the GTXE1s, the"RESETDONE" signal does not assert. Some internal signals (such as delay_RXUSRCLK and delay_RXUSRCLK2) also unexpectedly appear as 'X'
This issue has been found while performing a timing simulation on a Virtex-6 design using GTXE1 primitives using VCS-MX D-2009.12. Synopsys has been informed of this issue so it is addressed in a future release of the simulator.
To work around this issue, set thevcs option "-nohsopt". This switch disables an optimization algorithm that causes the issue.
For additional help on this topic, please contact Xilinx Technical Support (http://www.xilinx.com/support/clearexpress/websupport.htm)