In Virtex-6 DDR2/DDR3 designs produced with MIG 3.3, the placement (i.e. location) of some logic can prevent successful completion of Stage 2 Read Leveling during calibration. A failure in Read Leveling Stage 2 is denoted by dbg_rdvl_done[1:0] = 01. This issue will only be seen in hardware -- simulation will complete calibration successfully. The issue is related to the design's usage and placement of the Output Circular Buffer (OCB) Monitor used during OSERDES Clock Phase Calibration.For more information on the OCB Monitor, see The Virtex-6 FPGA Memory Interface User Guide. Details are in the DDR2 and DDR3 SDRAM Memory Interface Solution --> Core Architecture --> PHY section. Required work around steps are detailed in this answer record.
NOTE: Not all designs are affected by this issue since it is dependent on OCB monitor placement. Users should try the workaround detailed in this AR first. If the issue is still seen, please open a webcase for further support. All users MUST update to the MIG v3.4 Virtex-6 FPGA DDR2/DDR3 design which will be available with ISE design tools 12.1 in May. The workaround noted in this AR is only temporary. The fully implemented fix will be available with the v3.4 design.
If your design fails during stage 2 calibration, turn the OCB Monitor off and re-implement the design. This workaround has proven to work for most cases. This is a temporary workaround and should only be used until MIG v3.4 is available with ISE design tools 12.1.
Open the top-level MIG rtl module. This will be either 'example_design/rtl/ip_top/example_top.v/.vhd' or 'user_design/rtl/ip_top/core_name.v/.vhd'
Locate the OCB_MONITOR parameter and modify the setting from "ON" to "OFF":
parameter OCB_MONITOR = "ON",
parameter OCB_MONITOR = "OFF",
Re-implement the design and run the output bit-file in hardware. If calibration failures still exist, please open a webcase for further support.