General Description: The notes on pages 4-16 and 4-17 of the 9/96 Data Book and pages 4-13 and 4-15 of the 1/98 Data Book say:
"The pulse following the active edge of WCLK (Twps in Figure <#>) must be less than one millisecond wide. For most applications, this requirement is not overly restrictive; however, it must not be forgotten. Stopping WCLK at this point in the write cycle could result in excessive current and even cause damage to the large devices if many CLBs are configured as edge-triggered RAM."
These notes are misleading. They apply only to the XC4000E devices. In the 4000EX, 4000XL, 4000XV, and subsequent families, this problem has been resolved.