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AR# 34233

11.4i XST - How can I control the encoding style for an internal signal?


There is a 5-bit signal<para_case> inthe design, but it is changed to 20-bit after Synthesis. There are the following messages in Section "HDL Synthesis" in the Synthesis report.

Using one-hot encoding for signal <para_case>.
Found 20-bit register for signal <para_case>.

How can I prevent XST from using one-hot encoding for the signal?


For an internal signal, use signal_encoding constraint to control the encoding style that XST uses. Here is an example:

(*signal_encoding= "user"*)reg [4:0] para_case;

For detailed usage information of signal_encoding constraint, please refer to XST User Guide under design tools athttp://www.xilinx.com/support/
AR# 34233
Date 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
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