In the user application, the interrupt is sent to the core through the cfg_interrupt_* interface. However, the driver at the host is not reporting an interrupt request. Why is the interrupt accepted at the core but not sent to the host?
Note: This Answer Record is a part of the Xilinx Solution Center for PCI Express (Xilinx Answer 34536). The Xilinx Solution Center for PCI Express is available to address all questions related to PCIe. Whether you're starting a new design with PCIe or troubleshooting a problem, use the Solution Center for PCIe to guide you to the right information.
The MSI interrupt takes the form of a memory write request issued from the endpoint to the host. The endpoint needs to have its Bus Master enable bit set in order to send the Memory Write request transaction.
Please ensure that the Bus Master Enable bit is already set to 1 in the Command register in the PCI configuration space at addrexx 0x04. This register should be set by the host at device initialization.
This issue is more often seen in simulation because the testbench needs to enable the Bus Master Enable bit during the configuration process.
10/31/2011 - Initial Release