We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 34252

SPI-4.2 Lite v5.1 Rev2 - Virtex-6 FPGA block RAM resource utilization in v5.1 datasheet is not accurate


The block RAM count in the data sheet is not accurate for Virtex-6 FPGA. This is updated in the latest version of the data sheet released with v5.2 of the core in ISE design tools 12.1.


The correct block RAM utilization v5.1 Rev2 of the core is shown below:

   Block RAM
 64-bit Sink  3 (36k block RAM)
 1 (18k block RAM)
 32-bit Sink  2 (36k block RAM)
 1 (18k block RAM)
 64-bit Source  3 (36k block RAM)
 1 (18k block RAM)
 32-bit Source  2 (36k block RAM)
 1 (18k block RAM)

AR# 34252
Date 05/23/2014
Status Archive
Type General Article
  • SPI-4 Phase 2 Interface Solutions