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AR# 34280

Virtex-6 FPGA Integrated Block Wrapper v1.4 for PCI Express - Gen 1 Training Fails with 100 MHz reference clock


Gen 1 link training with 100 MHz reference clock might be sporadic due to problems in the MGT synchronization file (gtx_tx_sync_rate_v6.v[hd]).


An update is available in (Xilinx Answer 34279). Download the zip file titled "ar34279_v6_pcie_v1_4.zip" from this Answer Record.

This ZIP file contains a file called"gtx_tx_sync_rate_v6.v[hd]" which contains updated synchronization logic. Place this file in your generated core's source directory.

Note that this ZIP file is cumulative and might contain fixes for other problems, as described in(Xilinx Answer 34279).

Revision History

02/02/2010 - Initial Release

Linked Answer Records

Master Answer Records

AR# 34280
Date 05/22/2012
Status Active
Type Known Issues
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6 FPGA Integrated Block for PCI Express ( PCIe )
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