AR# 34284

MIG Design Assistant - Virtex-6 DDR2/DDR3 Simulation

Description

This section of the MIG Design Assistant focuses on Simulation of the Virtex-6 DDR3/DDR2 designs. Please select from the below options to find information related to your specific question.

Note: This Answer Record is a part of the Xilinx MIG Solution Center (Xilinx Answer 34243) The Xilinx MIG Solution Center is available to address all questions related to MIG. Whether you are starting a new design with MIG or troubleshooting a problem, use the MIG Solution Center to guide you to the right information.

Solution

Usage

MIG provides all files needed to simulate the memory interface in the output 'example_design/sim' and 'user_design/sim' directories. Included is:

Simulation testbench - sim_tb_top.v/.vhd
Memory models (provided for Micron only and only if License Agreement is accepted in the MIG tool)
ModelSim do script to run the functional simulation - sim.do

NOTE: At this time, timing simulation is not supported.

Speeding Up Simulation

Specific parameters are available to speed up simulation times. For more information, please see:

(Xilinx Answer 35747)

Debug (Xilinx Answer 34884) MIG Virtex-6 DDR2/DDR3 Simulation Debug

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Linked Answer Records

Associated Answer Records

Answer Number	Answer Title	Version Found	Version Resolved
34883	MIG Virtex-6 DDR2/DDR3 - Debugging issues with User Design simulations	N/A	N/A
34266	Xilinx Virtex-6 MIG Solution Center - Design Assistant	N/A	N/A
35747	MIG Virtex-6 DDR2/DDR3 - Speeding Up Simulation	N/A	N/A
34884	MIG Virtex-6 DDR2/DDR3 - Simulation Debug	N/A	N/A

AR# 34284
Date	12/15/2012
Status	Active
Type	General Article
Devices	Virtex-6 CXT Virtex-6 HXT Virtex-6 LX More Virtex-6 LXT Virtex-6 SXT Less
IP	MIG

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AR# 34284

MIG Design Assistant - Virtex-6 DDR2/DDR3 Simulation

Description

Solution

Linked Answer Records

Associated Answer Records

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