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AR# 34289

Device Power up Sequence

Description

What are the power sequencing requirements for FPGAs?

Solution

This is dependent on the specific architecture. Following is a compiled list of power sequencing requirements for Xilinx device architectures:

Virtex-6 FPGA

Virtex-6 devices require a power-on sequence of Vccint -> Vccaux -> Vcco. If the requirement cannot be met, then Vccaux must always be powered prior to Vcco. Vccaux and Vcco can be powered by the same supply. Therefore, both Vccaux and Vcco are permitted to ramp simultaneously. Similarly, for the power-down sequence, Vcco must be powered down prior to Vccaux. When powering down the device, using the recommended power sequence will ensure the I/Os are 3-stated during power ramp transitions.?

Virtex-5 FPGA

The device can be powered in any sequence. Xilinx recommends Vccint -> Vccaux -> Vcco. The I/O will remain 3-stated through power-on if the recommended power-on sequence is followed. The I/O current consumption might increase if the recommended sequence is not followed, but this should not be a reliability concern. Xilinx does not specify the current or I/O behavior for other power-on sequences. See DS202 for more information on this.

Virtex-4 FPGA

The device can be powered in any sequence. We recommend Vccint -> Vccaux -> Vcco. We do not characterize the current for any other power sequence. See the Virtex-4 family data sheet (DS302) for further information. Additionally, we do provide power-on current characterization data since the power-on current can potentially be greater than the normal device operating quiescent current.

Spartan-6 FPGA

The device can be powered in any sequence. We recommend Vccint -> Vccaux -> Vcco.

Spartan-3A/AN/DSP, Spartan-3E, Spartan-3 FPGA

The device can be powered in any sequence. We recommend Vccint -> Vccaux -> Vcco.
AR# 34289
Date Created 07/19/2010
Last Updated 01/11/2011
Status Active
Type General Article